Datasheet Details
| Part number | CY7C1308DV25 |
|---|---|
| Manufacturer | Cypress (now Infineon) |
| File Size | 659.29 KB |
| Description | 9-Mbit 4-Word Burst SRAM |
| Datasheet | CY7C1308DV25-CypressSemiconductor.pdf |
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Overview: CY7C1308DV25 9-Mbit 4-Word Burst SRAM with DDR-I Architecture.
| Part number | CY7C1308DV25 |
|---|---|
| Manufacturer | Cypress (now Infineon) |
| File Size | 659.29 KB |
| Description | 9-Mbit 4-Word Burst SRAM |
| Datasheet | CY7C1308DV25-CypressSemiconductor.pdf |
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• 9-Mbit density (256 Kbit x 36) • 167-MHz clock for high bandwidth • 4-Word Burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 333 MHz @ 167 MHz) • Two input clocks (K and K) for precise DDR timing—SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.
• Separate Port Selects for depth expansion • Synchronous internally self-timed writes • 2.5V core power supply with HSTL inputs and outputs • Available in 165-ball FBGA package (13 x 15 x 1.4 mm) • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–1.9V) • JTAG 1149.1 patible test access port Configuration CY7C1308DV25 – 256K x 36 The CY7C1308DV25 is a 2.5V Synchronous Pipelined SRAM equipped with DDR-I (Double Data Rate) architecture.
The DDR-I architecture consists of
| Part Number | Description |
|---|---|
| CY7C130 | 1K x 8 Dual-Port Static RAM |
| CY7C1302CV25 | 9-Mbit Burst of Two Pipelined SRAMs |
| CY7C1302DV25 | 9-Mbit Burst of Two Pipelined SRAMs |
| CY7C1303BV18 | 18-Mbit Burst of 2 Pipelined SRAM |
| CY7C1303BV25 | 18-Mbit Burst of Two-Pipelined SRAM |
| CY7C1304DV25 | 9-Mbit Burst of 4 Pipelined SRAM |
| CY7C1305BV18 | 18-Mbit Burst of 4 Pipelined SRAM |
| CY7C1305BV25 | 18-Mbit Burst of 4 Pipelined SRAM |
| CY7C1306BV18 | 18-Mbit Burst of 2 Pipelined SRAM |
| CY7C1307BV18 | 18-Mbit Burst of 4 Pipelined SRAM |