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CY7C1311JV18 - (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture

General Description

The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture.

QDR II architecture consists of two separate ports: the read port and the write port to access the memory array.

Key Features

  • CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 ® Configurations CY7C1311JV18.
  • 2M x 8 CY7C1911JV18.
  • 2M x 9 CY7C1313JV18.
  • 1M x 18 CY7C1315JV18.
  • 512K x 36 Separate Independent Read and Write Data Ports.
  • Supports concurrent transactions 300 MHz Clock for High Bandwidth 4-word Burst for reducing Address Bus Frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two Input Clocks (K and K).

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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18-Mbit QDR II SRAM 4-Word Burst Architecture Features ■ CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 ® Configurations CY7C1311JV18 – 2M x 8 CY7C1911JV18 – 2M x 9 CY7C1313JV18 – 1M x 18 CY7C1315JV18 – 512K x 36 Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions 300 MHz Clock for High Bandwidth 4-word Burst for reducing Address Bus Frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two Input Clocks (K and K) for Precise DDR Timing ❐ SRAM uses rising edges only Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems Single Multiplexed Address Input Bus latches Address Inputs for both Re