CY7C1311JV18 Overview
QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.
CY7C1311JV18 Key Features
- 2M x 8 CY7C1911JV18
- 2M x 9 CY7C1313JV18
- 1M x 18 CY7C1315JV18
- 512K x 36
- Supports concurrent transactions 300 MHz Clock for High Bandwidth 4-word Burst for reducing Address Bus Frequency Double