CY7C1315BV18 Datasheet | Cypress

CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features - Separate Independent Read and Write data ports - Supports concurrent transactions - 300-MHz clock for high bandwidth - 4-Word Burst for reducing address bus frequency - Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 600 MHz) at 300 MHz - Two input clocks (K and K) for precise DDR timing - SRAM uses rising edges only - Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches - Echo clocks (CQ and CQ) simplify data capture in high-speed systems - Single multiplexed address input bus latches address inputs for both Read and Write ports - Separate Port Selects for depth expansion - Synchronous internally self-timed writes - Available in x 8, x 9, x 18, and x 36 configurations - Full data coherency providing most current data - Core VDD = 1.8 (±0.1V); I/O VDDQ = 1.4V to VDD - Available in 165-ball FBGA package (13 x 15 x 1.4 mm) - Offered in both lead-free and non-lead free packages - Variable drive HSTL output buffers - JTAG 1149.1 patible test access port - Delay Lock Loop (DLL) for accurate data placement Functional Description The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to pletely eliminate the need to “turn-around” the data bus required with mon I/O devices. Access to each port is acplished through a mon address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II Read and Write ports are pletely independent of one...