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CY7C1315BV18 - (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture

This page provides the datasheet information for the CY7C1315BV18, a member of the CY7C1311BV18 (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture family.

Datasheet Summary

Description

The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.

QDR-II architecture consists of two separate ports to access the memory array.

Features

  • Separate Independent Read and Write data ports.
  • Supports concurrent transactions.
  • 300-MHz clock for high bandwidth.
  • 4-Word Burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 600 MHz) at 300 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock-skew and flight-.

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Datasheet preview – CY7C1315BV18

Datasheet Details

Part number CY7C1315BV18
Manufacturer Cypress Semiconductor
File Size 529.85 KB
Description (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
Datasheet download datasheet CY7C1315BV18 Datasheet
Additional preview pages of the CY7C1315BV18 datasheet.

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Full PDF Text Transcription

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CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth • 4-Word Burst for reducing address bus frequency • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 600 MHz) at 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-tim
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