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CY7C1315KV18 - 18-Mbit QDR II SRAM Four-Word Burst Architecture

This page provides the datasheet information for the CY7C1315KV18, a member of the CY7C1311KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture family.

Datasheet Summary

Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 333-MHz clock for high bandwidth.
  • Four-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two Input Clocks for Output Data (C and C) to minimize Clock skew and flight time mismatches.
  • Echo cl.

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Datasheet preview – CY7C1315KV18

Datasheet Details

Part number CY7C1315KV18
Manufacturer Cypress Semiconductor
File Size 657.31 KB
Description 18-Mbit QDR II SRAM Four-Word Burst Architecture
Datasheet download datasheet CY7C1315KV18 Datasheet
Additional preview pages of the CY7C1315KV18 datasheet.

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Full PDF Text Transcription

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 CY7C1311KV18/CY7C1911KV18 CY7C1313KV18/CY7C1315KV18 18-Mbit QDR® II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 333-MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two Input Clocks for Output Data (C and C) to minimize Clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Single multiplexed address input bus latches address inputs for read and write ports ■ Separate port selects
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