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CY7C1356C Datasheet 9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Manufacturer: Cypress (now Infineon)

Overview: CY7C1354C CY7C1356C 9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture 9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™.

Download the CY7C1356C datasheet PDF. This datasheet also includes the CY7C1354C variant, as both parts are published together in a single manufacturer document.

Key Features

  • Pin-compatible and functionally equivalent to ZBT.
  • Supports 250 MHz bus operations with zero wait states.
  • Available speed grades are 250, 200, and 166 MHz.
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE.
  • Fully registered (inputs and outputs) for pipelined operation.
  • Byte write capability.
  • Single 3.3 V power supply (VDD).
  • 3.3 V or 2.5 V I/O power supply (VDDQ).
  • Fast clock-to-output times.
  • 2.8 ns (for 250.