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CY7C1350G - 4-Mbit (128K x 36) Pipelined SRAM

General Description

The CY7C1350G is a 3.3 V, 128K × 36 synchronous-pipelined burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the inserti

Key Features

  • Pin compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Byte write capability.
  • 128K × 36 common I/O architecture.
  • 3.3 V power supply (VDD).
  • 2.5 V/3.3 V I/O power supply (VDDQ).
  • Fast clock-to-output times.
  • 2.8 ns (for 200-MHz device).
  • Clock enable (CEN) pin to suspend operation.
  • Synchronous self-timed writes.
  • Asynchronous output enable (OE).
  • Available in Pb.

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Other Datasheets by Cypress (now Infineon)

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1350G 4-Mbit (128K × 36) Pipelined SRAM with NoBL™ Architecture 4-Mbit (128K × 36) Pipelined SRAM with NoBL™ Architecture Features ■ Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need to use OE ■ Byte write capability ■ 128K × 36 common I/O architecture ■ 3.3 V power supply (VDD) ■ 2.5 V/3.3 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 2.