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CY7C1352 Datasheet 256k X18 Pipelined Sram

Manufacturer: Cypress (now Infineon)

Overview: .. CY7C1352 256K x18 Pipelined SRAM with NoBL™ Architecture.

General Description

The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

The CY7C1352 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.

This

Key Features

  • Pin compatible and functionally equivalent to ZBT™ devices MCM63Z818 and MT55L256L18P.
  • Supports 143-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Fully registered (inputs and outputs) for pipelined operation.
  • Byte Write Capability.
  • 256K x 18 common I/O architecture.
  • Single 3.3V power supply.
  • Fast clock-to-ou.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1352F 4-Mbit (256K x 18) Pipelined SRAM
CY7C1352G 4-Mbit (256K x 18) Pipelined SRAM
CY7C135 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM
CY7C1350G 4-Mbit (128K x 36) Pipelined SRAM
CY7C1351 128Kx36 Flow-Through SRAM
CY7C1351F 4-Mb (128K x 36) Flow-through SRAM
CY7C1351G 4-Mbit (128K x 36) Flow-Through SRAM
CY7C1353 256Kx18 Flow-Through SRAM
CY7C1353G 4-Mbit (256K x 18) Flow-Through SRAM
CY7C1354B 9-Mb (256K x 36/512K x 18) Pipelined SRAM

CY7C1352 Distributor