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CY7C1352 - 256K x18 Pipelined SRAM

General Description

The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

Key Features

  • Pin compatible and functionally equivalent to ZBT™ devices MCM63Z818 and MT55L256L18P.
  • Supports 143-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Fully registered (inputs and outputs) for pipelined operation.
  • Byte Write Capability.
  • 256K x 18 common I/O architecture.
  • Single 3.3V power supply.
  • Fast clock-to-ou.

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📁 Similar Datasheet

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1352F 4-Mbit (256K x 18) Pipelined SRAM
CY7C1352G 4-Mbit (256K x 18) Pipelined SRAM
CY7C135 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com CY7C1352 256K x18 Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices MCM63Z818 and MT55L256L18P • Supports 143-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-timed output buffer control to eliminate the need to use OE • Fully registered (inputs and outputs) for pipelined operation • Byte Write Capability • 256K x 18 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 4.0 ns (for 143-MHz device) — 4.2 ns (for 133-MHz device) — 5.0 ns (for 100-MHz device) — 7.