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CY7C1352G Datasheet 4-mbit (256k X 18) Pipelined Sram

Manufacturer: Cypress (now Infineon)

Overview: CY7C1352G 4-Mbit (256K × 18) Pipelined SRAM with NoBL™ Architecture 4-Mbit (256K × 18) Pipelined SRAM with NoBL™.

General Description

The CY7C1352G is a 3.3 V, 256K × 18 synchronous-pipelined burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states.

The CY7C1352G is equipped

Key Features

  • Pin compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Byte write capability.
  • 256K × 18 common I/O architecture.
  • 3.3 V core power supply (VDD).
  • 2.5 V/3.3 V I/O power supply (VDDQ).
  • Fast clock-to-output times.
  • 4.0 ns (for 133-MHz device).
  • Clock enable (CEN) pin to suspend operation.
  • Synchronous self-timed writes.
  • Asynchronous output enable (OE).
  • Available.

CY7C1352G Distributor