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CY7C1351G - 4-Mbit (128K x 36) Flow-Through SRAM

General Description

The CY7C1351G is a 3.3 V, 128K × 36 synchronous flow-through burst SRAM designed specifically to support unlimited tru

Key Features

  • Can support up to 133-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Pin compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow-through operation.
  • Byte write capability.
  • 128 K × 36 common I/O architecture.
  • 2.5 V/3.3 V I/O power supply (VDDQ).
  • Fast clock-to-output times.
  • 6.5 ns (for 133-MHz device).
  • Clock en.

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1351 128Kx36 Flow-Through SRAM
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1351G 4-Mbit (128K × 36) Flow-Through SRAM with NoBL™ Architecture 4-Mbit (128K × 36) Flow-Through SRAM with NoBL™ Architecture Features ■ Can support up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock ■ Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow-through operation ■ Byte write capability ■ 128 K × 36 common I/O architecture ■ 2.5 V/3.3 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 6.