Description
The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.
Features
- Pin compatible and functionally equivalent to ZBT™ devices IDT71V547, MT55L128L36F, and MCM63Z737.
- Supports 66-MHz bus operations with zero wait states.
- Data is transferred on every clock.
- Internally self-timed output buffer control to eliminate the need to use OE.
- Registered inputs for Flow-Through operation.
- Byte Write capability.
- 128K x 36 common I/O architecture.
- Single 3.3V power supply.
- Fast clock-to-output t.
CY7C1351 Datasheet
