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CY7C1351 - 128Kx36 Flow-Through SRAM

General Description

The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

Key Features

  • Pin compatible and functionally equivalent to ZBT™ devices IDT71V547, MT55L128L36F, and MCM63Z737.
  • Supports 66-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for Flow-Through operation.
  • Byte Write capability.
  • 128K x 36 common I/O architecture.
  • Single 3.3V power supply.
  • Fast clock-to-output t.

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📁 Similar Datasheet

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1351F 4-Mb (128K x 36) Flow-through SRAM
CY7C1351G 4-Mbit (128K x 36) Flow-Through SRAM
CY7C135 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM
CY7C1350G 4-Mbit (128K x 36) Pipelined SRAM
CY7C1352 256K x18 Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com CY7C1351 128Kx36 Flow-Through SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices IDT71V547, MT55L128L36F, and MCM63Z737 • Supports 66-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for Flow-Through operation • Byte Write capability • 128K x 36 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 11.0 ns (for 66-MHz device) — 12.0 ns (for 50-MHz device) • • • • • — 14.