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CY7C1367C - 9-Mbit Pipelined DCD Sync SRAM

Download the CY7C1367C datasheet PDF. This datasheet also covers the CY7C1366C variant, as both devices belong to the same 9-mbit pipelined dcd sync sram family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1366C/CY7C1367C SRAM i

Features

  • Supports bus operation up to 166 MHz.
  • Available speed grade is 166 MHz.
  • Registered inputs and outputs for pipelined operation.
  • Optimal for performance (double-cycle deselect).
  • Depth expansion without wait state.
  • 3.3 V.
  • 5% and + 10% core power supply (VDD).
  • 2.5 V/3.3 V I/O power supply (VDDQ).
  • Fast clock-to-output times.
  • 3.5 ns (for 166 MHz device).
  • Provide high performance 3-1-1-1 access rate.
  • User-selectable burst counter supp.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1366C-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C136 2K x 8 Dual-Port Static RAM
CY7C1360C 9-Mbit Pipelined SRAM
CY7C1360V25 256K x 36/256K x 32/512K x 18 Pipelined SRAM
CY7C1361C (CY7C1361C / CY7C1363C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1362C 9-Mbit Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1366C CY7C1367C 9-Mbit (256K × 36/512K × 18) Pipelined DCD Sync SRAM 9-Mbit (256K × 36/512K × 18) Pipelined DCD Sync SRAM Features ■ Supports bus operation up to 166 MHz ■ Available speed grade is 166 MHz ■ Registered inputs and outputs for pipelined operation ❐ Optimal for performance (double-cycle deselect) • Depth expansion without wait state ❐ 3.3 V – 5% and + 10% core power supply (VDD) ■ 2.5 V/3.3 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 3.
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