CY7C1420JV18 datasheet by Cypress (now Infineon).
This datasheet includes multiple variants, all published together in a single manufacturer document.
| Part number | CY7C1420JV18 |
|---|---|
| Datasheet | CY7C1420JV18 CY7C1418JV18 Datasheet (PDF) |
| File Size | 683.54 KB |
| Manufacturer | Cypress (now Infineon) |
| Description | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
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The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K.
View all Cypress (now Infineon) datasheets
| Part Number | Description |
|---|---|
| CY7C1420AV18 | (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1420BV18 | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1420KV18 | 36-Mbit DDR II SRAM Two-Word Burst Architecture |
| CY7C142 | 2K x 8 Dual-Port Static RAM |
| CY7C1421AV18 | 1.8V Synchronous Pipelined SRAM |
| CY7C1422AV18 | 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1422BV18 | 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1422JV18 | 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1423AV18 | 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1423BV18 | 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
