CY7C1420KV18 - 36-Mbit DDR II SRAM Two-Word Burst Architecture

This page provides the datasheet information for the CY7C1420KV18, a member of the CY7C1418KV18 36-Mbit DDR II SRAM Two-Word Burst Architecture family.

Product Overview

Cypress Semiconductor

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Datasheet Details

Part number	CY7C1420KV18
Manufacturer	Cypress Semiconductor
File Size	777.80 KB
Description	36-Mbit DDR II SRAM Two-Word Burst Architecture
Datasheet	CY7C1420KV18 Datasheet
Additional preview pages of the CY7C1420KV18 datasheet.

CY7C1420KV18 Product details

Description

The CY7C1418KV18, and CY7C1420KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture.

The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.

Features

36-Mbit density (2M × 18, 1M × 36).
333 MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simplify data capture in high speed systems.
Synchronous in.

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Published: Mar 14, 2017 |