CY7C1426JV18 Description
QDR-II architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support the read operations and the write port has dedicated data inputs to support the write operations. QDR-II architecture has separate data inputs and data outputs to pletely eliminate the need to “turn around” the data bus required with mon IO devices.
CY7C1426JV18 Key Features
- 4M x 8 CY7C1426JV18
- 4M x 9 CY7C1413JV18
- 2M x 18 CY7C1415JV18
- 1M x 36
- Supports concurrent transactions 300 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double