CY7C1426KV18 Datasheet 36-mbit Qdr Ii Sram Four-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1411KV18/CY7C1426KV18 CY7C1413KV18/CY7C1415KV18 36-Mbit QDR® II SRAM Four-Word Burst Architecture 36-Mbit QDR® II SRAM Four-Word Burst.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Datasheet Details

Part number	CY7C1426KV18
Manufacturer	Cypress (now Infineon)
File Size	1.28 MB
Description	36-Mbit QDR II SRAM Four-Word Burst Architecture
Datasheet	CY7C1426KV18 CY7C1411KV18 Datasheet (PDF)

Key Features

Separate independent read and write data ports.
Supports concurrent transactions.
333 MHz clock for high bandwidth.
Four-word burst for reducing address bus frequency.
Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo cl.

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More Datasheets from Cypress (now Infineon)

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CY7C1420JV18	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1420KV18	36-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1421AV18	1.8V Synchronous Pipelined SRAM
CY7C1422AV18	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture