CY7C1486BV25 - (CY7C148xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

This page provides the datasheet information for the CY7C1486BV25, a member of the CY7C1480BV25 (CY7C148xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM family.

Datasheet Summary

Description

The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

Features

Functional.

Cypress Semiconductor

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Datasheet Details

Part number	CY7C1486BV25
Manufacturer	Cypress Semiconductor
File Size	2.88 MB
Description	(CY7C148xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
Datasheet	CY7C1486BV25 Datasheet
Additional preview pages of the CY7C1486BV25 datasheet.

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Other Datasheets by Cypress Semiconductor

CY7C1486BV33 - (CY7C148xBV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
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CY7C1480BV25 - 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480BV33 - (CY7C148xBV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V33 - (CY7C1480V33 / CY7C1482V33 / CY7C1486V33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1481V25 - 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
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Full PDF Text Transcription

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CY7C1480BV25 CY7C1482BV25, CY7C1486BV25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ ■ ■ ■ ■ ■ Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

Published: Dec 9, 2010 |