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CY7C1486BV33 - (CY7C148xBV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

This page provides the datasheet information for the CY7C1486BV33, a member of the CY7C1480BV33 (CY7C148xBV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM family.

Datasheet Summary

Description

The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation.

Features

  • Functional.

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Datasheet preview – CY7C1486BV33

Datasheet Details

Part number CY7C1486BV33
Manufacturer Cypress Semiconductor
File Size 0.97 MB
Description (CY7C148xBV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
Datasheet download datasheet CY7C1486BV33 Datasheet
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  • CY7C1480BV25 - 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
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  • CY7C1480V33 - (CY7C1480V33 / CY7C1482V33 / CY7C1486V33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
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Full PDF Text Transcription

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CY7C1480BV33 CY7C1482BV33, CY7C1486BV33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ ■ ■ ■ ■ ■ Functional Description The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.
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