CY7C1512V18 - 1.8V Synchronous Pipelined SRAM

This page provides the datasheet information for the CY7C1512V18, a member of the CY7C1510V18 1.8V Synchronous Pipelined SRAM family.

Product Overview

Cypress Semiconductor

Part number	CY7C1512V18
Manufacturer	Cypress Semiconductor
File Size	389.43 KB
Description	1.8V Synchronous Pipelined SRAM
Datasheet	CY7C1512V18 Datasheet
Additional preview pages of the CY7C1512V18 datasheet.

Separate independent read and write data ports.
Supports concurrent transactions.
250 MHz clock for high bandwidth.
2-word burst on all accesses.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simp.

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Published: Nov 6, 2016 |