CY7C1521KV18 Description
CY7C1521KV18 72-Mbit DDR II SRAM Four-Word Burst Architecture 72-Mbit DDR II SRAM Four-Word Burst Architecture.
CY7C1521KV18 Key Features
- 72-Mbit Density (2M × 36)
- 250 MHz Clock for High Bandwidth
- Four-word Burst for reducing Address Bus Frequency
- Double Data Rate (DDR) Interfaces (data transferred at
- Two Input Clocks (K and K) for precise DDR Timing
- SRAM uses rising edges only
- Two Input Clocks for Output Data (C and C) to minimize Clock
- Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
- Synchronous Internally Self-timed Writes
- DDR II operates with 1.5 Cycle Read Latency when DOFF is