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CY7C1521V18 Datasheet 1.8v Synchronous Pipelined Sram

Manufacturer: Cypress (now Infineon)

Overview: CY7C1517V18 CY7C1528V18 CY7C1519V18 CY7C1521V18 72-Mbit DDR-II SRAM 4-Word Burst.

This datasheet includes multiple variants, all published together in a single manufacturer document.

General Description

• 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Synchronous internally self-timed writes • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–VDD) • Available in 165-ball FBGA package (15 x 17 x 1.4 mm) • Offered in lead-free and non lead-free packages • JTAG 1149.1 patible test access port • Delay Lock Loop (DLL) for accurate data placement

Key Features

  • Functional.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1521KV18 72-Mbit DDR II SRAM Four-Word Burst Architecture
CY7C1520KV18 72-Mbit DDR-II SRAM Two-Word Burst Architecture
CY7C1520V18 1.8V Synchronous Pipelined SRAM
CY7C1522AV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522JV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522KV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture
CY7C1522V18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1523AV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1523JV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1523KV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture

CY7C1521V18 Distributor