Datasheet4U Logo Datasheet4U.com

CY7C1568KV18 - 72-Mbit DDR II+ SRAM Two-Word Burst Architecture

Datasheet Summary

Features

  • 72-Mbit density (4M × 18, 2M × 36).
  • 550 MHz clock for high bandwidth.
  • Two-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz.
  • Available in 2.5 clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems.
  • Data valid pin (QVLD) to indicate valid data on the output.
  • Sync.

📥 Download Datasheet

Datasheet preview – CY7C1568KV18

Datasheet Details

Part number CY7C1568KV18
Manufacturer Cypress Semiconductor
File Size 623.41 KB
Description 72-Mbit DDR II+ SRAM Two-Word Burst Architecture
Datasheet download datasheet CY7C1568KV18 Datasheet
Additional preview pages of the CY7C1568KV18 datasheet.

📁 Similar Datasheet

  • CY7C1518AV18 - 72-Mbit DDR-II SRAM (Cypress)
  • CY7C1520AV18 - 72-Mbit DDR-II SRAM (Cypress)
  • CY7C1006D - 1-Mbit (256K x 4) Static RAM (Cypress)
  • CY7C1011G - 2-Mbit (128K words x 16 bit) Static RAM (Cypress)
  • CY7C1041G - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1041GE - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1041GN - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1049GN - 4-Mbit (512K words x 8 bit) Static RAM (Cypress)
  • CY7C1061DV33 - 16-Mbit (1 M X 16) Static RAM (Cypress)
  • CY7C1061G - 16-Mbit (1 M words x 16 bit) Static RAM (Cypress)
Other Datasheets by Cypress Semiconductor
  • CY7C1562XV18 - 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
  • CY7C15632KV18 - 72-Mbit QDR II+ SRAM Four-Word Burst Architecture
  • CY7C1563XV18 - 72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
  • CY7C1564XV18 - 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
  • CY7C1565KV18 - 72-Mbit QDR II+ SRAM Four-Word Burst Architecture
  • CY7C1565XV18 - 72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
  • CY7C150 - 1Kx4 Static RAM
  • CY7C1510AV18 - 72-Mbit QDR-II SRAM 2-Word Burst Architecture

Full PDF Text Transcription

Click to expand full text
CY7C1568KV18/CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ 72-Mbit density (4M × 18, 2M × 36) ■ 550 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz ■ Available in 2.5 clock cycle latency ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Data valid pin (QVLD) to indicate valid data on the output ■ Synchronous internally self-timed writes ■ DDR II+ operates with 2.
Published: |