CY7C2565XV18 Datasheet | Cypress

CY7C2563XV18/CY7C2565XV18 72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features - Separate independent read and write data ports - Supports concurrent transactions - 633 MHz clock for high bandwidth - Four-word burst for reducing address bus frequency - Double data rate (DDR) interfaces on both read and write ports (data transferred at 1266 MHz) at 633 MHz - Available in 2.5 clock cycle latency - Two input clocks (K and K) for precise DDR timing - SRAM uses rising edges only - Echo clocks (CQ and CQ) simplify data capture in high-speed systems - Data...