CY7C2561KV18 Description
Similar to QDR-II architecture, QDR-II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.
CY7C2561KV18 Key Features
- 8M x 8 CY7C2576KV18
- 8M x 9 CY7C2563KV18
- 4M x 18 CY7C2565KV18
- 2M x 36
- Supports concurrent transactions 550 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double
- SRAM uses rising edges only Echo clocks (CQ and CQ) simplify data capture in high-speed systems Data valid pin (QVLD) to
- Supports both 1.5V and 1.8V IO supply HSTL inputs and variable drive HSTL output buffers Available in 165-Ball FBGA pack
- Functional Description