Datasheet4U Logo Datasheet4U.com

CY7C2563KV18 - 72-Mbit QDR-II SRAM 4-Word Burst Architecture

This page provides the datasheet information for the CY7C2563KV18, a member of the CY7C2561KV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture family.

Datasheet Summary

Description

The CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and CY7C2565KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II+ architecture.

Similar to QDR-II architecture, QDR-II+ architecture consists of two separate ports: the read port and the write port to access the memory array.

Features

  • Configurations With Read Cycle Latency of 2.5 cycles: CY7C2561KV18.
  • 8M x 8 CY7C2576KV18.
  • 8M x 9 CY7C2563KV18.
  • 4M x 18 CY7C2565KV18.
  • 2M x 36 Separate independent read and write data ports.
  • Supports concurrent transactions 550 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz Available in 2.5 clock cycle latency Two inp.

📥 Download Datasheet

Datasheet preview – CY7C2563KV18

Datasheet Details

Part number CY7C2563KV18
Manufacturer Cypress Semiconductor
File Size 915.19 KB
Description 72-Mbit QDR-II SRAM 4-Word Burst Architecture
Datasheet download datasheet CY7C2563KV18 Datasheet
Additional preview pages of the CY7C2563KV18 datasheet.

📁 Similar Datasheet

  • CY7C225 - 512 x 8 Registered PROM (Cypress)
  • CY7C277 - 32K x 8 Reprogrammable Registered PROM (Cypress)
  • CY7C008 - 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
  • CY7C008V - 3.3V 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
  • CY7C009 - 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
  • CY7C009V - 128K x 8 Dual-Port Static RAM (Cypress)
  • CY7C018 - 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
  • CY7C018V - 3.3V 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
  • CY7C019 - 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
  • CY7C019V - 3.3V 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
Other Datasheets by Cypress Semiconductor
  • CY7C25632KV18 - 72-Mbit QDR II+ SRAM Four-Word Burst Architecture
  • CY7C2563XV18 - 72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
  • CY7C2561KV18 - 72-Mbit QDR-II SRAM 4-Word Burst Architecture
  • CY7C2562XV18 - 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
  • CY7C2564XV18 - 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
  • CY7C25652KV18 - 72-Mbit QDR II+ SRAM Four-Word Burst Architecture
  • CY7C2565KV18 - 72-Mbit QDR-II SRAM 4-Word Burst Architecture
  • CY7C2565XV18 - 72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture

Full PDF Text Transcription

Click to expand full text
www.DataSheet.co.kr PRELIMINARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 72-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features ■ Configurations With Read Cycle Latency of 2.5 cycles: CY7C2561KV18 – 8M x 8 CY7C2576KV18 – 8M x 9 CY7C2563KV18 – 4M x 18 CY7C2565KV18 – 2M x 36 Separate independent read and write data ports ❐ Supports concurrent transactions 550 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz Available in 2.
Published: |