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CY7C2563XV18 Datasheet 72-mbit Qdr Ii+ Xtreme Sram Four-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C2563XV18/CY7C2565XV18 72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.

CY7C2563XV18 datasheet preview

Datasheet Details

Part number	CY7C2563XV18
Manufacturer	Cypress (now Infineon)
File Size	1.19 MB
Description	72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
Datasheet	CY7C2563XV18-CypressSemiconductor.pdf

Key Features

Separate independent read and write data ports.
Supports concurrent transactions.
633 MHz clock for high bandwidth.
Four-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces on both read and write ports (data transferred at 1266 MHz) at 633 MHz.
Available in 2.5 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed sy.

CY7C2563XV18 Distributor

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Part Number	Description
CY7C25632KV18	72-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C2563KV18	72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C2561KV18	72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C2562XV18	72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C2564XV18	72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C25652KV18	72-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C2565KV18	72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C2565XV18	72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
CY7C25682KV18	72-Mbit DDR II+ SRAM Two-Word Burst Architecture
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