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CY7C2564XV18 Datasheet 72-mbit Qdr Ii+ Xtreme Sram Two-word Burst Architecture

Manufacturer: Cypress (now Infineon)

This datasheet includes multiple variants, all published together in a single manufacturer document.

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 450 MHz clock for high bandwidth.
  • Two-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz.
  • Available in 2.5 clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high-speed syst.

CY7C2564XV18 Distributor

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C2561KV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C2562XV18 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C25632KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C2563KV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C2563XV18 72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
CY7C25652KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C2565KV18 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C2565XV18 72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
CY7C25682KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C25422KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture