CY7C25632KV18 - 72-Mbit QDR II+ SRAM Four-Word Burst Architecture

Datasheet Summary

Features

Separate independent read and write data ports.
Supports concurrent transactions.
550 MHz clock for high bandwidth.
Four-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz.
Available in 2.5 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed sy.

Cypress Semiconductor

📥 Download Datasheet

Datasheet Details

Part number	CY7C25632KV18
Manufacturer	Cypress Semiconductor
File Size	608.41 KB
Description	72-Mbit QDR II+ SRAM Four-Word Burst Architecture
Datasheet	CY7C25632KV18 Datasheet
Additional preview pages of the CY7C25632KV18 datasheet.

📁 Similar Datasheet

CY7C225 - 512 x 8 Registered PROM (Cypress)
CY7C277 - 32K x 8 Reprogrammable Registered PROM (Cypress)
CY7C008 - 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
CY7C008V - 3.3V 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
CY7C009 - 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
CY7C009V - 128K x 8 Dual-Port Static RAM (Cypress)
CY7C018 - 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
CY7C018V - 3.3V 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
CY7C019 - 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
CY7C019V - 3.3V 64K/128K x 8/9 Dual-Port Static RAM (Cypress)

Other Datasheets by Cypress Semiconductor

CY7C2563KV18 - 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C2563XV18 - 72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
CY7C2561KV18 - 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C2562XV18 - 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C2564XV18 - 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C25652KV18 - 72-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C2565KV18 - 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C2565XV18 - 72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture

Full PDF Text Transcription

Click to expand full text

CY7C25632KV18 CY7C25652KV18 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 550 MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz ■ Available in 2.

Published: Mar 14, 2017 |