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CY7C4021KV13 - 72-Mbit QDR-IV HP SRAM

Key Features

  • 72-Mbit density (4M ×18, 2M ×36).
  • Total Random Transaction Rate [1] of 1334 MT/s.
  • Maximum operating frequency of 667 MHz.
  • Read latency of 5.0 clock cycles and Write latency of 3.0 clock cycles.
  • Two-word burst on all accesses.
  • Dual independent bi-directional data ports.
  • Double data rate (DDR) data ports.
  • Supports concurrent read/write transactions on both ports.
  • Single address port used to control both data ports.
  • DDR address signaling.
  • Sing.

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C402 (CY7C401 - CY7C404) 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO
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CY7C4041KV13 72-Mbit QDR-IV HP SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C4021KV13/CY7C4041KV13 72-Mbit QDR™-IV HP SRAM 72-Mbit QDR™-IV HP SRAM Features ■ 72-Mbit density (4M ×18, 2M ×36) ■ Total Random Transaction Rate [1] of 1334 MT/s ■ Maximum operating frequency of 667 MHz ■ Read latency of 5.0 clock cycles and Write latency of 3.0 clock cycles ■ Two-word burst on all accesses ■ Dual independent bi-directional data ports ❐ Double data rate (DDR) data ports ❐ Supports concurrent read/write transactions on both ports ■ Single address port used to control both data ports ❐ DDR address signaling ■ Single data rate (SDR) control signaling ■ High-speed transceiver logic (HSTL) and stub series terminated logic (SSTL) ❐ I/O VDDQ = 1.2 V ± 50 mV or 1.25 V ± 50 mV ■ Pseudo open drain (POD) signaling (JESD8-24 compliant) ❐ I/O VDDQ = 1.1 V ± 50 mV or 1.