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CY7C4041KV13 - 72-Mbit QDR-IV HP SRAM

Download the CY7C4041KV13 datasheet PDF. This datasheet also covers the CY7C4021KV13 variant, as both devices belong to the same 72-mbit qdr-iv hp sram family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • 72-Mbit density (4M ×18, 2M ×36).
  • Total Random Transaction Rate [1] of 1334 MT/s.
  • Maximum operating frequency of 667 MHz.
  • Read latency of 5.0 clock cycles and Write latency of 3.0 clock cycles.
  • Two-word burst on all accesses.
  • Dual independent bi-directional data ports.
  • Double data rate (DDR) data ports.
  • Supports concurrent read/write transactions on both ports.
  • Single address port used to control both data ports.
  • DDR address signaling.
  • Sing.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C4021KV13-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C408A 64 x 8 Cascadable FIFO Cypress
CY7C409A 64 x 9 Cascadable FIFO Cypress
CY7C419 256/512/1K/2K/4K x 9 Asynchronous FIFO Cypress
CY7C4221 1 K / 2 K x 9 Synchronous FIFOs Cypress
CY7C4231 1 K / 2 K x 9 Synchronous FIFOs Cypress

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C404 (CY7C401 - CY7C404) 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO
CY7C401 (CY7C401 - CY7C404) 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO
CY7C402 (CY7C401 - CY7C404) 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO
CY7C4021KV13 72-Mbit QDR-IV HP SRAM
CY7C403 (CY7C401 - CY7C404) 64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C4021KV13/CY7C4041KV13 72-Mbit QDR™-IV HP SRAM 72-Mbit QDR™-IV HP SRAM Features ■ 72-Mbit density (4M ×18, 2M ×36) ■ Total Random Transaction Rate [1] of 1334 MT/s ■ Maximum operating frequency of 667 MHz ■ Read latency of 5.0 clock cycles and Write latency of 3.0 clock cycles ■ Two-word burst on all accesses ■ Dual independent bi-directional data ports ❐ Double data rate (DDR) data ports ❐ Supports concurrent read/write transactions on both ports ■ Single address port used to control both data ports ❐ DDR address signaling ■ Single data rate (SDR) control signaling ■ High-speed transceiver logic (HSTL) and stub series terminated logic (SSTL) ❐ I/O VDDQ = 1.2 V ± 50 mV or 1.25 V ± 50 mV ■ Pseudo open drain (POD) signaling (JESD8-24 compliant) ❐ I/O VDDQ = 1.1 V ± 50 mV or 1.