CY7C4265 Datasheet | Cypress

16K × 18 Deep Sync FIFOs 16K × 18 Deep Sync FIFOs Features - High speed, low power, first-in first-out (FIFO) memories - 16K × 18 (CY7C4265) - 0.5 micron CMOS for optimum speed and power - High speed 100 MHz operation (10 ns read/write cycle times) - Low power - ICC = 45 m A - Fully asynchronous and simultaneous read and write operation - Empty, full, half full, and programmable almost empty and almost full status flags - TTL patible - Retransmit function - Output enable (OE) pins - Independent read and write enable pins - Center power and ground pins for reduced noise - Supports free-running 50 percent duty cycle clock inputs - Width and depth expansion capability - 64-pin TQFP and 64-pin STQFP - Pb-free packages available Logic Block Diagram Functional Description The CY7C4265 are high speed, low power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally patible...