CY7C4282V Datasheet | Cypress

.. CY7C4282V CY7C4292V 64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion Features - 3.3V operation for low power consumption and easy integration into low-voltage systems - High-speed, low-power, first-in first-out (FIFO) memories - 64K x 9 (CY7C4282V) - 128K x 9 (CY7C4292V) - 0.35 micron CMOS for optimum speed/power - High-speed, Near Zero Latency (True Dual-Ported Memory Cell), 100-MHz operation (10 ns read/write cycle times) - Low power - ICC = 25 m A - - - - - - - - - - - ISB = 6 m A Fully asynchronous and simultaneous read and write operation Empty, Full, and Programmable Almost Empty and Almost Full status flags Retransmit function Output Enable (OE ) pin Independent read and write enable pins Supports free-running 50% duty cycle clock inputs Width Expansion Capability Depth Expansion Capability through token-passing scheme (no external logic required) 64-pin 10x10 STQFP Pin-patible 3.3V solution for CY7C4282/92 Functional Description The CY7C4282V/92V are high-speed, low-power, first-in firstout (FIFO) memories with clocked read and write interfaces. All devices are 9 bits wide. The CY7C4282V/92V can be cascaded to increase FIFO depth. Programmable Features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, video and munications buffering. These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and a Write Enable pin (WEN). Retransmit and Synchronous Almost Full/Almost Empty flag Features are available on these devices. Depth expansion is possible using the Cascade Input (XI), Cascade Output (XO), and First Load (FL) pins. The XO pin is connected to the XI pin of the next device, and the XO pin of the last device should be connected to the XI pin of the first device. The FL pin of...