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CY7C451 - (CY7C451 - CY7C454) Cascadable Colcked FIFOs

Description

The CY7C451, CY7C453, and CY7C454 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read Logic Block Diagram D0 8 Pin Configurations INPUT REGISTER CKW ENW FLAG/PARITY PROGRAM REGISTER PLCC/LCC Top View D0 D1 D2 D3 D4 D5 D6 PARITY WRITE CONTROL FLAG LOGIC R

Features

  • High-speed, low-power, first-in first-out (FIFO) memories.
  • 512 x 9 (CY7C451).
  • 2,048 x 9 (CY7C453).
  • 4,096 x 9 (CY7C454).
  • 0.65 micron CMOS for optimum speed/power.
  • High-speed 83-MHz operation (12 ns read/write cycle time).
  • Low power.
  • ICC=70 mA.
  • Fully asynchronous and simultaneous read and write operation.
  • Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags.
  • TTL compati.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C453 (CY7C451 - CY7C454) Cascadable Colcked FIFOs
CY7C454 (CY7C451 - CY7C454) Cascadable Colcked FIFOs
CY7C455 (CY7C455 - CY7C457) Cascadable Colcked FIFOs
CY7C456 (CY7C455 - CY7C457) Cascadable Colcked FIFOs
CY7C457 (CY7C455 - CY7C457) Cascadable Colcked FIFOs

Full PDF Text Transcription

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54 CY7C451 CY7C453 CY7C454 512x9, 2Kx9, and 4Kx9 Cascadable Clocked FIFOs with Programmable Features • High-speed, low-power, first-in first-out (FIFO) memories • 512 x 9 (CY7C451) • 2,048 x 9 (CY7C453) • 4,096 x 9 (CY7C454) • 0.
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