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CYF2018V - 18/36/72-Mbit Programmable Multi-Queue FIFOs

Description

The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device.

It has independent read and write ports, which can be clocked up to 100 MHz.

User can configure input and output bus sizes.

Features

  • Functional.

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CYF2018V, CYF2036V CYF2072V 18/36/72-Mbit Programmable Multi-Queue FIFOs 18/36/72-Mbit Programmable Multi-Queue FIFOs Features ■ Functional Description The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 100 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 3.6 Gbps. The read and write ports can support multiple I/O voltage standards. The user-programmable registers enable user to configure the device operation as desired. The device also offers a simple and easy-to-use interface to reduce implementation and debugging efforts, improve time-to-market, and reduce engineering costs.
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