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W163 - Spread Aware/ Zero Delay Buffer

General Description

Reference Input: The output signals Q0:3 will be synchronized to this signal unless the device is programmed to bypass the PLL.

Outputs: These signals will be synchronous and of equal frequency to the signal input at pin 1.

Key Features

  • Spread Aware™.
  • designed to work with SSFTG reference signals.
  • Outputs may be three-stated.
  • Available in 8-pin SOIC package.
  • Extra strength output drive available (-15 version).
  • Internal feedback maximized the number of outputs available in 8-pin package Key Specifications Operating Voltage: 3.3V±10% Operating Range: 10 < fOUT < 133 MHz Cycle-to-Cycle Jitter: 200 ps Output-to-Output Skew: 250 ps Device-to-Device Skew: 700 ps Propagation De.

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Other Datasheets by Cypress (now Infineon)

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W161 133-MHz Spread Spectrum FTG
W162 Spread Aware/ Zero Delay Buffer
W164 Spread Spectrum Desktop/Notebook System Frequency Generator
W166 Spread Spectrum Frequency Timing Generator
W167B 133-MHz Spread Spectrum FTG

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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W163 Spread Aware™, Zero Delay Buffer Features • Spread Aware™—designed to work with SSFTG reference signals • Outputs may be three-stated • Available in 8-pin SOIC package • Extra strength output drive available (-15 version) • Internal feedback maximized the number of outputs available in 8-pin package Key Specifications Operating Voltage: ................................................ 3.3V±10% Operating Range: ................................ 10 < fOUT < 133 MHz Cycle-to-Cycle Jitter: .................................................. 200 ps Output-to-Output Skew: .............................................. 250 ps Device-to-Device Skew:............................................... 700 ps Propagation Delay: ......................................................