W163 Overview
The output signals Q0:3 will be synchronized to this signal unless the device is programmed to bypass the PLL. These signals will be synchronous and of equal frequency to the signal input at pin 1. This output signal does not vary from signals Q0:3 in function, but is noted as the signal used to establish the propagation delay of nearly.
W163 Key Features
- Spread Aware™-designed to work with SSFTG reference signals
- Outputs may be three-stated
- Available in 8-pin SOIC package
- Extra strength output drive available (-15 version)
- Internal feedback maximized the number of outputs available in 8-pin package
- 3.3V±10% Operating Range
- 10 < fOUT < 133 MHz Cycle-to-Cycle Jitter
- 200 ps Output-to-Output Skew
- 250 ps Device-to-Device Skew
- 700 ps Propagation Delay