Datasheet Summary
25/0251
Features
- True Dual-Ported memory cells which allow simultaneous access of the same memory location
- 64K x 8 organization (CY7C008)
- 128K x 8 organization (CY7C009)
- 64K x 9 organization (CY7C018)
- 128K x 9 organization (CY7C019)
- 0.35-micron CMOS for optimum speed/power
- High-speed access: 15/20/25 ns
- Low operating power
- Active: ICC = 115 mA (typical)
- Standby: ISB3 = 10 µA (typical)
Logic Block Diagram
R/WL CE0L CE1L
CY7C008V/009V CY7C018V/019V
3.3V 64K/128K x 8/9 Dual-Port Static RAM
- Fully asynchronous operation
- Automatic power-down
- Expandable data bus to 16/18 bits or more using Mas- ter/Slave chip select when using more than one device
- On-chip...