CY7C1461KV33 Datasheet

CY7C1461KV33 Key Features

• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
• Supports up to 133 MHz bus operations with zero wait states
• Data is transferred on every clock
• Pin patible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the need to use OE
• Registered inputs for flow through operation
• Byte write capability
• 3.3 V and 2.5 V I/O power supply
• Fast clock-to-output times
• 6.5 ns (for 133-MHz device)