DMP1008UCA9 Description
This 3rd generation Lateral MOSFET (LD-MOS) is engineered to minimize on-state losses and switch ultra-fast, making it ideal for high efficiency power transfer. It uses Chip-Scale Package (CSP) to increase power density by bining low thermal impedance with minimal RDS(ON) per footprint area. LD-MOS Technology with the Lowest Figure of Merit:.
DMP1008UCA9 Key Features
- LD-MOS Technology with the Lowest Figure of Merit
- RDS(ON) = 5.7mΩ to Minimize On-State Losses
- Qg = 9.5nC for Ultra-Fast Switching
- VGS(TH) = -0.7V Typ. for a Low Turn-On Potential
- CSP with Footprint 1.5mm x 1.5mm
- Height = 0.34mm for Low Profile
- ESD Protection of Gate
- Totally Lead-Free & Fully RoHS pliant (Notes 1 & 2)
- Halogen and Antimony Free. “Green” Device (Note 3)