DS26503 Datasheet | Dallas Semiconducotr

DESCRIPTION The DS26503 is a building-integrated timingsupply (BITS) clock-recovery element. The receiver portion can recover a clock from T1, E1, and 6312k Hz synchronization timing interfaces. In T1 and E1 modes, the Synchronization Status Message (SSM) can also be recovered. The transmit portion can directly interface to T1 or E1 interfaces as well as source the SSM in T1 and E1 modes. The DS26503 can translate between any of the supported inbound synchronization clock rates to any supported outbound rate. A separate output is provided to source a 6312k Hz clock. The device is controlled through a parallel, serial, or hardware controller port. FEATURES - G.703 2048k Hz Synchronization Interface pliant - G.703 6312k Hz Japanese Synchronization Interface pliant - Interfaces to Standard T1/J1 (1.544MHz) and E1 (2.048MHz) - Interface to CMI-Coded T1/J1 and E1 - Short- and Long-Haul Line Interface - Transmit and Receive T1 and E1 SSM Messages with Message Validation - Crystal-Less Jitter Attenuator with Bypass Mode - Fully Independent Transmit and Receive Functionality - Internal Software-Selectable Receive- and Transmit-Side Termination for .. 75Ω/100Ω/110Ω/120Ω - Monitor Mode for Bridging Applications APPLICATIONS - Accepts 16.384MHz, 8.192MHz, 4.096MHz, BITS Timing 2.048MHz, or 1.544MHz (T1 Only) Master Rate Conversion Clock Basic Transceiver - 8-Bit Parallel Control Port, Multiplexed or Nonmultiplexed, Intel or Motorola - Serial (SPI) Control Port ORDERING INFORMATION - Hardware Control Mode PART TEMP RANGE PIN-PACKAGE - Provides LOS, AIS, and LOF Indications DS26503L 0°C to +70°C 64 LQFP Through Hardware Output Pins - Fast Transmitter-Output Disable Through DS26503LN -40°C to +85°C 64 LQFP Device Pin for Protection Switching - IEEE 1149.1 JTAG Boundary Scan - 3.3V Supply with 5V-Tolerant Inputs and Outputs Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be...