3D7010G Datasheet | Data Delay Devices

3D7010 MONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D7010) Features - - - - - - - - - - - All-silicon, low-power CMOS technology- TTL/CMOS patible inputs and outputs Vapor phase, IR and wave solderable Auto-insertable (DIP package) Low ground bounce noise Leading- and trailing-edge accuracy Delay range: 8 through 500ns Delay tolerance: 5% or 2ns Temperature stability: ±3% typical (0C-70C) Vdd stability: ±2% typical (4.75V-5.25V) Minimum input pulse width: 20% of total delay IN N/C O2 O4 O6 O8 GND 1 2 3 4 5 6 7 PACKAGES 14 13 12 11 10 9 8 VDD O1 O3 O5 O7 O9 O10 IN N/C N/C O2 O4 O6 O8 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD N/C O1 O3 O5 O7 O9 O10 3D7010 DIP 3D7010G Gull-Wing 3D7010S SOL (300 Mil) For mechanical dimensions, click here. FUNCTIONAL DESCRIPTION The 3D7010 10-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 8ns through 50ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D7010 is TTL- and CMOSpatible, capable of driving ten 74LS-type loads, and Features both rising- and falling-edge accuracy. The all-CMOS 3D7010 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 16-pin SOIC. PIN DESCRIPTIONS IN O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 VDD GND Delay Line Input Tap 1 Output (10%) Tap 2 Output (20%) Tap 3 Output (30%) Tap 4 Output (40%) Tap 5 Output (50%) Tap 6 Output (60%) Tap 7 Output (70%) Tap 8 Output (80%) Tap 9 Output (90%) Tap 10 Output (100%) +5 Volts Ground .. TABLE 1: PART NUMBER SPECIFICATIONS PART NUMBER DIP-14 SOIC-16 3D7010 3D7010S 3D7010G -80 -80 -90 -90 -100 -100 -150 -150 -200 -200 -250 -250 -300 -300 -400 -400 -500 -500...