3D7105 Datasheet | Data Delay Devices

Features - - - - - - - - - - - - data 3 ® delay devices, inc. PACKAGES IN N/C N/C O2 N/C O4 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD N/C O1 N/C O3 N/C O5 IN 1 8 VDD All-silicon, low-power CMOS VDD IN 1 8 O2 2 7 O1 technology O4 3 6 O3 O1 O2 2 7 GND 4 5 O5 TTL/CMOS patible O3 O4 3 6 inputs and outputs 3D7105Z O5 GND 4 5 SOIC Vapor phase, IR and wave (150 Mil) solderable 3D7105M DIP Auto-insertable (DIP pkg.) 3D7105H Gull-Wing (300 Mil) Low ground bounce noise Leading- and trailing-edge accuracy IN 1 16 VDD Delay range: .75 through 80ns N/C 2 15 N/C Delay tolerance: 5% or 1ns N/C 3 14 N/C O2 4 13 O1 Temperature stability: ±3% typical (0C-70C) N/C 5 12 N/C O4 6 11 O3 Vdd stability: ±1% typical (4.75V-5.25V) N/C 7 10 N/C GND 8 9 O5 Minimum input pulse width: 30% of total delay 14-pin DIP and 16-pin SOIC available as drop-in 3D7105S SOIC replacements for hybrid delay lines (300 Mil) 3D7105 DIP 3D7105G Gull-Wing 3D7105K Unused pins removed (300 Mil) FUNCTIONAL DESCRIPTION The 3D7105 5-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 0.75ns through 8.0ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D7105 is TTL- and CMOSpatible, capable of driving ten 74LS-type loads, and Features both rising- and falling-edge accuracy. PIN DESCRIPTIONS IN O1 O2 O3 O4 O5 VCC GND N/C Delay Line Input Tap 1 Output (20%) Tap 2 Output (40%) Tap 3 Output (60%) Tap 4 Output (80%) Tap 5 Output (100%) +5 Volts Ground No Connection The all-CMOS 3D7105 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC. TABLE 1: PART NUMBER SPECIFICATIONS PART NUMBER DIP-8 3D7105M 3D7105H SOIC-8 3D7105Z...