3D7110 Datasheet | Data Delay Devices

.. MONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D7110) Features PACKAGES IN N/C O2 O4 O6 O8 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD O1 O3 O5 O7 O9 O10 - - - - - - - - - - - - All-silicon, low-power CMOS technology IN 1 14 VDD TTL/CMOS patible inputs and outputs N/C 2 13 O1 Vapor phase, IR and wave solderable O2 3 12 O3 Auto-insertable (DIP pkg.) O4 4 11 O5 Low ground bounce noise Leading- and trailing-edge accuracy O6 5 10 O7 Delay range: .75 through 80ns O8 6 9 O9 Delay tolerance: 5% or 1ns GND 7 8 O10 Temperature stability: ±3% typical (0C-70C) 3D7110 DIP Vdd stability: ±1% typical (4.75V-5.25V) 3D7110G Gull-Wing Minimum input pulse width: 15% of total delay 14-pin Gull-Wing and 16-pin SOIC available as drop-in replacements For mechanical dimensions, click here. for hybrid delay lines For package marking details, click here. 3D7110D SOIC (150 Mil) IN N/C N/C O2 O4 O6 O8 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD N/C O1 O3 O5 O7 O9 O10 3D7110S SOL (300 Mil) FUNCTIONAL DESCRIPTION The 3D7110 10-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 0.75ns through 8.0ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D7110 is TTL- and CMOSpatible, capable of driving ten 74LS-type loads, and Features both rising- and falling-edge accuracy. The all-CMOS 3D7110 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 14-pin auto-insertable DIP and space saving surface mount 14- and 16-pin SOIC packages. PIN DESCRIPTIONS IN O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 VDD GND Delay Line Input Tap 1 Output (10%) Tap 2 Output (20%) Tap 3 Output (30%) Tap 4 Output (40%) Tap 5 Output (50%) Tap 6 Output (60%) Tap 7 Output...