Datasheet4U Logo Datasheet4U.com

PI6CB184Q - 4-Output PCIe Gen 4 Clock Buffer

General Description

The PI6CB184Q is an 4-output very low power PCIe Gen1/Gen2/ Gen3/Gen4 clock buffer.

It takes an reference input to fanout four 100MHz low power differential HCSL outputs with on-chip terminations.

The on-chip termination can save 16 external resistors and make layout easier.

Key Features

  • ÎÎ1.8V supply voltage ÎÎHCSL input: 100MHz, also suppport 50MHz or 125MHz via SMBus ÎÎ4 differential low power HCSL outputs with on-chip termination ÎÎIndividual output enable ÎÎProgrammable Slew rate and output amplitute for each output ÎÎDifferential outputs blocked until PLL is locked ÎÎStrapping pins or SMBus for configuration; ÎÎ3.3V tolerant SMBus interface support ÎÎVery low jitter outputs yyDifferential cycle-to-cycle jitter.

📥 Download Datasheet

Other Datasheets by Diodes Incorporated

Part Number Description
PI6CB332000 20-Output PCIe 4.0/5.0/6.0 Clock Buffer
PI6CB332004A 4-Output Low-Power Fanout Clock Buffer
PI6CB33201 Very-Low-Power Two-Output PCIe Clock Buffer
PI6CB332012A 12-Output Low-Power Fanout Clock Buffer
PI6CB33202 Very-Low-Power Two-Output PCIe Clock Buffer
PI6CB33402 Very Low Power 4-Output PCIe Clock Buffer
PI6CB33802 Very-Low-Power 8-Output PCIe Clock Buffer
PI6CBE33123 Low-Power 12-Output ZDB / Fanout Clock Buffer
PI6C39X0202 Low Skew 1 to 2 Clock Buffer
PI6C4931504-04 High Performance HCSL Fanout Buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Pb Lead-free Green A product Line of Diodes Incorporated PI6CB184Q 4-Output PCIe Gen 4 Clock Buffer for Automotive Applications Features ÎÎ1.8V supply voltage ÎÎHCSL input: 100MHz, also suppport 50MHz or 125MHz via SMBus ÎÎ4 differential low power HCSL outputs with on-chip termination ÎÎIndividual output enable ÎÎProgrammable Slew rate and output amplitute for each output ÎÎDifferential outputs blocked until PLL is locked ÎÎStrapping pins or SMBus for configuration; ÎÎ3.3V tolerant SMBus interface support ÎÎVery low jitter outputs yyDifferential cycle-to-cycle jitter <50ps yyDifferential output-to-output skew <50ps yyPCIe Gen1/Gen2/Gen3/Gen4 compliant ÎÎAEC-Q 100 qualified, Automotive Grade 2 support ÎÎTotally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) ÎÎHalogen and Antimony Free.