EDI81256P Datasheet | EDI

Zl EDI 256Kx1 Static RAM CMOS, High Speed Monolithic EDI81256CIP35145155 High Speed 256K Monolithic SRAM Features The EDI81256C/P is a262,144 bit high performance, low power CMOS Static RAM organized as 256Kx1. It is available in Standard (C) and Low Power (P) versions. Fully asynchronous, the EDI81256C/P requires no clocks or refreshing for operation. All inputs and outputs are TTLpatible and operate from a single 5volt supply. Military product is available 100% screened to MILSTD-883C, Class B. 256Kx1 bit CMOS Static Random Access Memory - Access Times 35, 45, and 55ns - Fully Static, No Clocks - Inputs and Outputs Directly TTL patible - Data Retention Function on ED181256P Jedec Approved Pinouts - 24 Pin Ceramic DIP (0) - 28 Pin Ceramic LCC (L) Single +5V (±10%) Supply Operation Pin Configuration and Block Diagram A0 1 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 010 W11 VSS 12 24 vee 23 A17 22 A16 21 A15 20 A14 19 A13 18 A12 17 A11 16 A10 15 A9 14 D 13 E NO A3 A4 AS A6 A7 9 AS 10 all NO 12 13 14 15 16 17 WVSS E 0 A9 (1) Pin Names ~0-A17 D a VCC...