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EDI8464P - High Speed 256K Monolithic SRAM

This page provides the datasheet information for the EDI8464P, a member of the EDI8464C High Speed 256K Monolithic SRAM family.

Datasheet Summary

Features

  • The EDI8464C/P is ahigh performance CMOS Static 64Kx4 bit CMOS Static RAM organized as 64Kx4 and available in both standard Random Access Memory power (C) and low power (P) versions. Inputs and.
  • Access Times 35, 45 and 55 ns outputs are TTL compatible and allow for direct.
  • Fully Static, No Clocks interfacing with common system bus architecture.
  • Inputs and Outputs Directly TTL Compatible The EDI8464C/P is packaged in a28 Pin LCC, which.
  • Data Retention F.

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Datasheet preview – EDI8464P

Datasheet Details

Part number EDI8464P
Manufacturer EDI
File Size 333.08 KB
Description High Speed 256K Monolithic SRAM
Datasheet download datasheet EDI8464P Datasheet
Additional preview pages of the EDI8464P datasheet.

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Full PDF Text Transcription

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~EDI 64Kx4 Static RAM CMOS, High Speed Monolithic EDI8464CIP35145155 High Speed 256K Monolithic SRAM Features The EDI8464C/P is ahigh performance CMOS Static 64Kx4 bit CMOS Static RAM organized as 64Kx4 and available in both standard Random Access Memory power (C) and low power (P) versions. Inputs and • Access Times 35, 45 and 55 ns outputs are TTL compatible and allow for direct • Fully Static, No Clocks interfacing with common system bus architecture. • Inputs and Outputs Directly TTL Compatible The EDI8464C/P is packaged in a28 Pin LCC, which • Data Retention Function on EDI8464P provides excellent board level packing densities. (For a Jedec Approved Pinouts 64Kx4 in a 24 Pin DIP package refer to EDI8465C/P.
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