EDI8465P Datasheet | EDI

~EDI 64Kx4 Static RAM CMOS, High Speed Monolithic EDI8465CIP35145155 High Speed 256K Monolithic SRAM Features The EDI8465C/P is a high performance CMOS Static RAM organized as 64Kx4 and available in both standard power (C) and low power (P) versions. Inputs and outputs are TTL patible and allow for direct interfacing with mon system bus architecture. The EDI8465C/P is packaged in a300 mil wide, 24 pin DIP, which provides excellent board level packing densities. Military product is available 100% screened to MILSTD-883C, Class B. 64Kx4 bit CMOS Static Random Access Memory - Access Times 35, 45, and 55ns - Fully Static, No Clocks - Data Retention Function on EDI8465P - Battery Back-up Capability - TTL patilbe I/O Jedec Approved Pinout - 24 Pin Ceramic DIP, 300 mils wide (0) - mon Data Inputs and Outputs Single +5V (±10%) Supply Operation Pin Configuration and Block Diagram A0 1 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 A910 E11 VSS 12 24 vee 23 A15 22 A14 21 A13 20 A12 19 A11 18 A10 17 D03 16 D02 15 D01 14 D00 13 W ROW DECOOE AS AS AA KJ A2 A. A- - A.4 MEMORY ARRAY 8 BLOCKS 256 ROWS 32 COLUMNS 4 BITS WIDE Pin...