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F50D2G41XA - 1.8V 2-Gbit SPI-NAND Flash Memory

General Description

Serial peripheral interface (SPI) NAND is an SLC NAND Flash memory device that provides a cost-effective nonvolatile memory storage solution where pin count must be kept to a minimum.

It is also an alternative solution to SPI NOR, offering superior write performance and cost per bit over SPI NOR.

Key Features

  • Single-level cell (SLC) technology.
  • Organization - Page size x1: 2176 bytes (2048 + 128 bytes) - Block size: 64 pages (128K + 8K bytes) - Device size: 2Gb (2 planes, 1024 blocks per plane).
  • Standard and extended SPI-compatible serial bus interface - Instruction, address on 1 pin; data out on 1, 2, or 4 pins - Instruction on 1 pin; address, data out on 2 or 4 pins - Instruction, address on 1 pin; data in on 1 or 4 pins.
  • User-selectable internal ECC supported - 8 bits/512 byte.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ESMT Flash FEATURES  Single-level cell (SLC) technology  Organization - Page size x1: 2176 bytes (2048 + 128 bytes) - Block size: 64 pages (128K + 8K bytes) - Device size: 2Gb (2 planes, 1024 blocks per plane)  Standard and extended SPI-compatible serial bus interface - Instruction, address on 1 pin; data out on 1, 2, or 4 pins - Instruction on 1 pin; address, data out on 2 or 4 pins - Instruction, address on 1 pin; data in on 1 or 4 pins  User-selectable internal ECC supported - 8 bits/512 bytes  Array performance - 104 MHz clock frequency (MAX) - Page read: 30μs (MAX) with on-die ECC disabled; 80μs (MAX) with on-die ECC enabled - Page program: 200μs (TYP) with on-die ECC disabled; 220μs (TYP) with on-die ECC enabled - Block erase: 2ms (TYP)  Advanced features - Read page cache mode