Download F50L1G41LC Datasheet PDF
F50L1G41LC page 2
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F50L1G41LC Key Features

  • Voltage Supply: 3.3V (2.7V~3.6V)
  • Organization
  • Memory Cell Array: (128M + 4M) x 8bit
  • Data Register: (2K + 64) x 8bit
  • Automatic Program and Erase
  • Page Program: (2K + 64) Byte
  • Block Erase: (128K + 4K) Byte
  • Page Read Operation
  • Page Size: (2K + 64) Byte
  • Read from Cell to Register with Internal ECC: 100us

F50L1G41LC Description

Serial peripheral interface (SPI) NAND is an SLC NAND Flash memory device that provides a cost-effective nonvolatile memory storage solution where pin count must be kept to a minimum. It is also an alternative solution to SPI NOR, offering superior writes performance and cost per bit over SPI NOR. The hardware interface creates a low pincount device with a standard pinout that remains the same from one density to...