F59D4G81KA Overview
The device has 4352-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 4352-byte increments. The Erase operation is implemented in a single block unit (256Kbytes + 16Kbytes). The device is a memory device which utilizes the I/O pins for both address and data input/output as well as mand inputs.
F59D4G81KA Key Features
- Voltage Supply VCC: 1.8V (1.7 V ~ 1.95V)
- Automatic Program and Erase Page Program: (4K + 256) bytes Block Erase: (256K + 16K) bytes
- Page Read Operation Random Read: 25us (Max.) Read Cycle: 45ns
- Write Cycle Time Page Program Time: 400us (Typ.) 700us (Max.) Block Erase Time: 3.5 ms (Typ.) 10ms (Max.)
- 1bit/cell
- mand/Address/Data Multiplexed DQ Port
- Hardware Data Protection
- Reliable CMOS Floating Gate Technology
- mand Register Operation
- Number of partial program cycles in the same page (NOP): 4
