M12L128168A-5BVG2N Datasheet | Elite Semiconductor Microelectronics Technology

ESMT SDRAM Features - JEDEC standard 3.3V power supply - LVTTL patible with multiplexed address - Four banks operation - MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) - All inputs are sampled at the positive going edge of the system clock - Burst Read single write operation - DQM for masking - Auto & self refresh (self refresh is not supported for VA grade) - Refresh - 64ms refresh period (4K cycle) for V grade - 16ms refresh period (4K cycle) for VA grade M12L128168A (2N) Automotive Grade 2M x 16 Bit x 4 Banks Synchronous DRAM GENERAL DESCRIPTION The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Product ID Max Freq. Automotive range (V): -40℃ to +85℃ M12L128168A-5TVG2N 200MHz 200MHz...