M12L128168A-6BIG2S Datasheet | Elite Semiconductor Microelectronics Technology

Features - JEDEC standard 3.3V power supply - LVTTL patible with multiplexed address - Four banks operation - MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) - All inputs are sampled at the positive going edge of the system clock - Burst Read single write operation - DQM for masking - Auto & self refresh - 64ms refresh period (4K cycle) M12L128168A (2S) Operation Temperature Condition -40°C~85°C 2M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION Product ID M12L128168A-5TIG2S M12L128168A-5BIG2S M12L128168A-6TIG2S M12L128168A-6BIG2S M12L128168A-7TIG2S M12L128168A-7BIG2S Max Freq. Package ments 200MHz 54 Pin TSOPII Pb-free 200MHz 54 Ball FBGA Pb-free 166MHz 54 Pin TSOPII Pb-free 166MHz 54 Ball FBGA Pb-free 143MHz 54 Pin TSOPII Pb-free 143MHz 54 Ball FBGA Pb-free GENERAL DESCRIPTION The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. PIN CONFIGURATION (TOP VIEW) (TSOPII 54L, 400mil X875mil Body, 0.8mm Pin Pitch) BALL CONFIGURATION (TOP VIEW) (BGA 54, 8mm X8mm X1mm Body, 0.8mm Ball Pitch) Elite Semiconductor Microelectronics Technology Inc. Publication Date: Mar. 2017 Revision: 1.0 1/45 mand Decoder Control Logic Row Decoder Latch Circuit Input & Output Buffer ESMT BLOCK...